The present invention relates to the storage of digital data on magnetic media. More specifically, the invention relates to the use of a partial response, maximum likelihood (PRML) recording channel in a tape drive.
Partial response signaling has been used extensively in digital data communication systems. Its potential applicability to digital magnetic recording was noted in 1970 in an article by Kubayshi entitled Application of Partial-Response Channel Coding to Magnetic Recording Systems, IBM Journal of Research and Development, January 1971, pp. 64-74. Although partial response signaling was soon applied experimentally in the recording channels of hard disk drives (see, for example, Price et al., An Experimental, Multilevel, High Density Disk Recording System IEEE Transactions on Magnetics, Vol. 14, No. 5, September 1978), commercial applications in this area have only recently been developed. Disk based PRML systems are described, for example, in U.S. Pat. No. 5,422,760 to Abbott et al., and U.S. Pat. No. 5,430,768 to Minuhin et al. The disclosures of the two above described articles and two above described patents are hereby incorporated by reference in their entirety.
In a partial response, maximum likelihood recording channel, the data is encoded onto the media at a rate which produces a high degree of intersymbol interference. This intersymbol interference, which would prevent accurate decoding in a peak detection system, is interpreted with a low bit error rate by a bit decoder which decodes the bit stream in the context of the previously interpreted bits. As is demonstrated by the literature and current interest in partial response signaling in magnetic recording, this method of data recording produces substantially improved channel utilization, although at the expense of a more complicated detection and decoding circuit.
It is well known that Class IV (PR4) partial response signaling is well suited to magnetic recording. Certain magnetic tape systems are especially suited to the use of the Extended Class IV (EPR4) system, characterized by the polynomial 1+Dxe2x88x92D2xe2x88x92D3, wherein xe2x80x9cDxe2x80x9d denotes the one bit delay operator. During the read operation, the analog read voltage is sampled by an analog to digital converter which is synchronized in phase and frequency with the incoming bit stream. With EPR4 signaling, discrimination of the digitized read voltage results in a five level output stream (often denoted as +2, +1, 0, xe2x88x921, xe2x88x922) which is decoded by the maximum likelihood decoder into a serial output of recorded bits.
Although the spectral response of some head/tape interfaces are suited to EPR4 signaling, there are additional problems when using maximum likelihood decoders with tape media that are not present in disk drives. The most significant of these is the high degree of instantaneous speed variation (ISV) of the tape. In disk based systems, the speed of the media under the read head is far more stable than it is with tape. Tape stretching and slippage in a tape drive recording apparatus cause the detected bit rate to vary substantially.
High levels of ISV pose problems because in both peak detection systems and partial response systems a phase-locked-loop must substantially synchronize the sampling by the analog to digital converter to the incoming bit stream. In a peak detection system, phase errors are computed by monitoring the slope of the read signal at the sampling time. The phase and frequency of ADC sampling is corrected if sampling is offset from the transition induced peaks where the read waveform has a zero slope. In partial response systems, phase errors are calculated by comparing sampled read signal amplitudes with the amplitudes expected at that sample time for the given decoded bit stream. In both cases, the calculated phase error is typically converted into an analog voltage or current signal with a digital to analog converter. This analog phase error signal is input to a current or voltage controlled oscillator which in turn controls the sample times of the analog to digital converter which is monitoring the read signal.
To accurately decode an analog read signal produced by a read head in a magnetic data storage device, therefore, the read signal should include phase information which is easily detectable by the phase locked loop to produce feedback which ensures accurate tracking. Furthermore, the phase information contained in the read signal should be quickly converted into a timing correction to minimize the lag between timing error detection and timing error correction.
The first concern, ensuring adequate phase content in the analog read signal, may be addressed by coding the data stream such that long strings of 1s, 0s, or other patterns producing a low read signal amplitude in the data sequence are prevented. Due to high levels of ISV, tape drive recording channels have typically been implemented using relatively inefficient block codes. This has limited the data density of magnetic tape systems considerably.
The second concern, reducing the delay between timing error detection and correction, has also remained insufficiently addressed. When partial response signaling is used, the problem is especially acute because the timing window in which the analog to digital sampling must occur for reliable decoding is much narrower than with peak detect systems. High levels of ISV therefore pose greater problems with partial response channels than with peak detecting channels, and this factor has limited the application of partial response coding to digital tape storage. Although the phase-locked-loop will resynchronize the analog to digital sampling to the incoming bit phase and frequency in response to variations in tape speed, the loop filtering, digital to analog conversion, and oscillator control typically introduce a rather lengthy delay before timing is completely restored.
The present invention is directed to digital gain and timing control in a magnetic recording system. The invention is particularly applicable to magnetic recording systems in which media speed variations are relatively large, such as in magnetic tape systems. A completely digital timing control circuit reduces delays and other problems associated with timing control that includes analog feedback circuitry.
In one embodiment, the invention includes a tape drive for storing data on magnetic tape comprising write electronics including a variable rate encoder, wherein the variable rate encoder is configured to insert bits into a received data stream at a rate which depends on the content of the data stream. The tape drive may also comprise a write head for writing the data stream including the inserted bits to linear tracks on a magnetic tape as well as read electronics for reading the data stream from the magnetic tape. The read electronics may comprise a digital timing feedback loop for maintaining phase lock with the data stream. In some embodiments, the variable rate encoder satisfies a (0,k) run length limited code constraint.
A further aspect of the present invention includes sampling an analog read signal at a frequency higher than the bit rate of the data bits being read. Accordingly, the invention also comprises a partial response, maximum likelihood recording channel comprising read electronics and an analog, to digital converter for periodically sampling an analog read waveform, wherein the frequency of sampling is substantially constant, and is predetermined to be greater than the bit rate of the received encoded serial bit stream. In such a system, timing control may be accomplished without a voltage or current controlled oscillator.
Methods of maintaining phase lock in partial response read channels are also provided. In one embodiment, such a method comprises computing a read signal amplitude error in a partial response bit decoder; digitally filtering the amplitude error to define a timing error metric, and modifying the computation of an interpolated read signal amplitude in response to the timing error metric.